The present invention relates to power semiconductor devices having a MOS gate, as used in inverters and the like.
Insulated gate bipolar transistors (hereinafter referred to as "IGBT") and power MOS field effect transistors (hereinafter referred to as "MOSFET") are voltage driven type semiconductor switching devices used widely in power electronics because of their low on-voltage and high switching speed.
An IGBT-output type inverter device may have an overcurrent flow into the IGBT if there is an inrush current when a motor is activated, and failures such as a load short circuit and arm short circuit occur. Hence, superior electric characteristics are required for protecting the IGBT against the high voltage and current, including a breakdown withstand capability known as a "short-circuit withstand capability."
Inverter devices usually include a protection circuit to detect the occurrence of short-circuit failures, and to turn the power supply off. Such a protection circuit requires 10 to 20 .mu.sec to detect the overcurrent and to effect its protective function. The IGBT must be protected against breakdown during this time.
Many recent high-performance IGBT modules adopt an overcurrent-protection system which is disposed independently of the protection circuit in the inverter device. Such an overcurrent-protection system can quickly detect an overcurrent flowing into the IGBT when a short-circuit failure occurs, can limit the current in the IGBT, and can suppress it to within the short-circuit withstand capacity of the elements by means of a gate control based on this overcurrent detection signal before the power supply is turned off by the protection circuit.
FIG. 6 shows an IGBT overcurrent-protection circuit according to this protection system. Connected in parallel with main element 1 (IGBT) is a current-detection sub-element 2 (IGBT further to the main element 1). The sub-element 2 is also connected in series to a current-detection resistance 3. A switching element 4 (MOSFET) is connected to the gate-driving circuits for the main element 1 and the sub-element 2 to perform on-off operation according to the voltage generated between the two ends of the current-detection resistance 3.
When an overcurrent due to load short-circuit failure or the like flows into the main element 1 and the sub-element 2 and causes the voltage between the ends of the current-detection resistance 3 to exceed the threshold voltage of the switching element 4, the switching element 4 turns on to reduce the gate voltage of both the main element 1 and the current-detection sub-element 2, thus limiting the main current flowing in the main element 1. Thus, the main current can be lowered to within the short-circuit withstand capability of the element 1 by means of adequately setting the resistance of the current-detection resistance 3 and the threshold voltage of the switching element 4.
FIG. 7 is a wave chart showing a main current I.sub.D and a voltage V.sub.D across the main element 1 at the power supply voltage of 400 V while the protective circuit of FIG. 6 limits an overcurrent caused by load short-circuit fault. In FIG. 7, the main element 1 is an IGBT rated at 600 V and 100 A, externally connected to the above-described protective circuit. As shown in FIG. 7, the main current I.sub.D of the IGBT is limited within a few microseconds to about 250 A corresponding to the short-circuit withstand capability set with respect to the rated current of 100 A. It is difficult to maintain the ratio between the operations of the elements 1 and 2 because of the temperature difference between the chips on which the elements 1 and 2 are individually mounted. To solve this problem, a configuration has been proposed wherein the elements 1 and 2 are formed on a common chip.
For example, U.S. Pat. No. 4,783,690 addresses the problem of the temperature difference between the elements 1 and 2 by assigning some of the cells constituting a main MOSFET a role as sensing cells for overcurrent detection, and by leading out from the sensing cells an electrode for overcurrent detection. The following problems remain in this structure: First, the actual ratio between the main current and the current for overcurrent detection deviates from the desired value since a current leaks through a parasitic lateral MOSFET caused between the main and the sensing cell portions. And, since the main cells and the sensing cell portions are adjoining, a leakage current is caused by minority carriers between the main and sensing cell portions. This leakage current further causes deviation of the actual ratio between the main current and the current for overcurrent detection from the desired value.
To solve these problems, the present applicant has disclosed in the above-identified U.S. patent application Ser. No. 08/397,417 a method for reducing the leakage current by expanding the spacing between the main and the sensing cell portions.
FIG. 8 is a sectional view showing an exemplary IGBT device according to the above-identified U.S. Patent Application. A p-type base region 9 is formed selectively at the surface of an n-type base layer 8. An n-type emitter region 10 is formed at the surface of the p-type base region 9. A gate electrode 12 connected to a terminal G is fixed via a gate oxide film 11 to the surface of the portion of the p-type base region 9 extending between the n-type base layer 8 and the n-type emitter region 10. An emitter electrode is fixed via an insulating film 20 to the surface of the device. The emitter electrode is divided into an emitter electrode 14 for a main cell portion 6 and an emitter electrode 15 for a sensing cell portion 7. The emitter electrode 14 is connected to a terminal E and the emitter electrode 15 is connected to a terminal M. A collector electrode 16 connected to a terminal C is fixed to the back surface of a semiconductor substrate 5. The main cell portion 6 and the sensing cell portion 7, delimited by channel regions 13 of the main and sensing cell portions 6 and 7, are spaced by a spacing L of 100 .mu.m or more, long enough to prevent mutual interference between the main and sensing cell portions 6 and 7. A p-type well 17, to which is fixed the emitter electrode 14 of the main cell portion 6, is formed between the main and sensing cell portions 6 and 7 to capture the minority carriers (holes).
The device of FIG. 8 does not fully solve the problems with the device of U.S. Pat. No. 4,783,690. Also, the following problems remain to be addressed: First, if large spaces are placed between the main and sensing cell portions to prevent the leakage current, chip area and cost are increased. Further, the sensing cell portion of a MOS semiconductor devices having a main cell portion and a sensing cell portion may break down upon disconnection of the current detecting resistor when a high voltage is applied between the source and drain or between the collector and emitter in the off-state of the device.
This breakdown is illustrated in FIGS. 9(a) and 9(b). FIG. 9(a) is a circuit diagram showing an equivalent circuit of the IGBT having the main cell portion 6 and the sensing cell portion 7. In FIG. 9(a), a high voltage is applied between the collector and emitter of the IGBT, while the emitter terminal M is in the open state. FIG. 9(b) is a sectional view of the IGBT in which the main cell portion 6 and the sensing cell portion 7 adjoin one another. In FIGS. 9(a) and 9(b), the voltage between the collector and the emitter (between the terminals C and E, and between the terminals C and M) of the main cell portion 6 and the sensing cell portion 7 is determined by the collector potential when the junction leakage currents I.sub.RE and I.sub.RM flow. Since the emitter electrode 14 of the main cell portion is grounded while the emitter electrode 15 of the sensing cell portion is open, the potential of the emitter electrode 15 rises gradually. In response to this potential rise, the voltage between the emitter terminal M and the gate terminal G of the sensing cell portion rises. When the voltage between the terminals M and G greatly exceeds the withstand voltage of the gate oxide film 11, the gate oxide film 11 finally breaks down at "x" in FIG. 9(b).
Another problem lies in that a spike noise voltage may occur across the current detecting resistor at the instance when the MOS semiconductor device is turned on.
This spike noise voltage is illustrated in FIGS. 10(a) and 10(b). FIG. 10(b) is a circuit diagram showing an equivalent circuit of the IGBT which is connected to a load and turned on and off. In FIG. 10(b), a resistor R.sub.S for detecting a current I.sub.C is connected between the emitter terminals M and E of the sensing and main cell portions 7 and 6. The current I.sub.C is measured by detecting a voltage V.sub.S across the resistor R.sub.S. FIG. 10(a) is a graph showing gate voltage V.sub.G, the current I.sub.C, and the detecting voltage V.sub.S during the operation of the circuit of FIG. 10(b). Though the voltage V.sub.S should be proportional to the current I.sub.C, a spike noise is caused on the voltage V.sub.S at the turn-on of the IGBT. The spike noise is caused by the capacitance between the gate electrode 12 and the emitter terminal 15 of the sensing cell portion 7. In response to the rapid rise of the gate voltage V.sub.G at the turn-on of the IGBT, a displacement current I.sub.GM flows through the capacitor C.sub.GM : EQU I.sub.GM =C.sub.GM .multidot.dV.sub.G /dt
The current I.sub.GM gives rise to a voltage V.sub.S across the resistor R.sub.S : EQU V.sub.S =I.sub.GM .multidot.R.sub.S =C.sub.GM .multidot.R.sub.S dV.sub.G /d t
Accordingly, the voltage is proportional to the capacitance C.sub.GM between the gate electrode 12 and the emitter electrode 15 of the sensing cell portion 7, and the rising rate of the gate voltage V.sub.G.